1. Field of the Invention
This invention relates to detecting location of bit fails in a memory array, and particularly to bit failure (bit fail) mapping of an embedded memory system employing Array Built-In Self-Test (ABIST) to detect bit fails.
2. Description of Background
A number of different methods currently exist to diagnose scan chain failures in an electronic chip. See, for example, U.S. Pat. No. 3,761,695 of Eichelberger for “Method of Level Sensitive Testing a Functional Logic System”; U.S. Pat. No. 6,308,290 B1 of Forlenza et al. for “Look Ahead Scan Chain Diagnostic Method”; U.S. Pat. No. 6,643,807 of Heaslip et al, for “Array-Built-In-Self-Test (ABIST) for Efficient, Fast, Bitmapping of Large Embedded Arrays in Manufacturing Test”; U.S. Pat. No. 7,010,735 by Motika et al. for “Stuck-At Fault Scan Chain Diagnostic Method”; U.S. Pat. No. 7,017,095 of Forlenza et al. for Diagnostic Method for Detection of Multiple Defects in a Level Sensitive Scan Design (LSSD); U.S. Pat. No. 7,159,145 of Wang et al, for “Built-In Self Test System and Method”; and U.S. Pat. No. 7,225,374 of Burdine for “ABIST-Assisted Detection of Scan Chain Effects”; all owned by the assignee of the present invention and incorporated herein by reference.
Typically, however, no one method is by itself sufficient to diagnose a scan chain fail in a chip with enough confidence to send it to the Physical Failure Analysis (PFA) function of analyzing the failure to determine the cause thereof and to correct the process for making the chip to prevent that particular failure in future runs. These methods are self-contained entities, and are not structured to interface with one another. Much time is spent in determining which method(s) to utilize and in exercising these methods manually. Even if a method is automated via a software medium (i.e. in a computer system), nevertheless, manual intervention is required to determine which method(s) to use, to capture the results from each method, and to analyze the results from each method to determine which device to send to PFA.
Substantial amounts of time on the order of days, and sometimes weeks are required in order to diagnose a sufficient number of failing devices to send to a device to PFA. During the days and weeks of delay, the manufacturing fabrication line (fab) continues to produce products which are likely to contain the same defects. Therefore, yields often remain low, which results in significant cost-impacts. Thus, it is critical that failing parts should be diagnosed as quickly as possible to minimize the amount of defective product that continues to be processed through a wafer fabrication (fab) facility.
U.S. Pat. No. 7,206,979 of Zarrineh et al. for “Method and Apparatus for “At-Speed Diagnostics of Embedded Memories” describes a method of testing an embedded memory which includes providing a programmable memory module and using the programmable memory BIST module to extract contents of the embedded memory upon detection of an error. The programmable memory BIST module includes a pseudo binary search and stop on error function.
U.S. published pat. appl. No. 2005/0120270 by Anand et al, (cited above) points out that as embedded memory sizes, overall BIST (Built In Self Test) testing time increases; so novel schemes that reduce test time while maintaining test integrity and diagnostic resolution are desirable. One issue is that ATE (Automated Test Equipment) tester clock, is not fast enough to accommodate BIST testing. This can be addressed by having the BIST run off an internal clock that is a multiplied frequency of the ATE tester clock. However, the ability to accurately bit fail map a memory that is tested by an internal multiplied clock is inhibited by the inability to stop the test circuitry at the exact point when a fail is encountered, shift out the fail data, and then resume the test successfully.
Anand et al. describes a bit fail map circuit which accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed ATE tester. The high speed multiplied clock is generated by an on-chip clock multiplier which multiplies the external clock. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps. The method identifies the bit-mapped fault detected by at-speed execution, when an on-chip clock multiplier is used for testing. Anand et al U.S. Pat. Publication also states that use of BIST helps to alleviate the capital cost of a high performance ATE, however at the expense of silicon overhead, and that on chip clock frequency multiplication (PLL's, DLL's, etc.) enables at-speed BIST testing with a low cost, low-speed tester. On-chip memories can thus be tested at-speed with a low-speed ATE tester.
Wang et al, U.S. Pat. No. 7,159,145 (above) describes prior art on the inclusion of a structure and method in an integrated circuit which includes read/write memory, for the support of an ABIST. Wang et al shows a structure in an integrated circuit that includes a read/write memory and describes a method for the support of an ABIST.
The general method is depicted in FIG. 1 which is a block diagram of a prior art ABIST configuration 100 for detecting location of bit fails in a memory array, and particularly to bit fail mapping of an embedded memory system employing ABIST to detect bit fails in the memory array. A test controller supplies a scan input to an ABIST controller 200. The ABIST Controller 200 exercises the memory element 210, and a pipeline 230 which supply expected results to an ABIST Results Register 220 with a Scan Out line 222. The pipeline uses common clocks 120 to supply inputs to the to the ABIST Results Register 220 in a staged timing path which aligns the expected data to the Results Register 220, with the actual data from the Memory element 210. Conventional clocks 120 are supplied to the ABIST Controller 200, the pipeline 230, and the ABIST Results Register 220.
The ABIST Controller 200, is used to exercise the memory array 210, and pipeline 230 expected results to the results register 220. The function of the pipeline 230, is to provide a timed path delay for the expected results data from the ABIST Controller 200, to compensate for the propagation delay of the data from the memory array 210 to the results register 220. The results register 220 compares the data from the Memory Element 210 and the expected data generated by the ABIST Controller 200. If the data does not match, an error has occurred and the Real Time Fail (RTF 30) flag is set, out of the ABIST results register 220.
Heaslip et al, U.S. Pat. No. 6,643,807 (above) describes detecting failed cycles at a Real Time Fail Pin (RTFP). Heaslip et al also describes a method of identifying failing cells of a bad memory element, bitmapping the array, which is facilitated by sending a Real Time Fail (RTF) indicator on line 30 to an external system, when a fault is detected as n.